Ken Choi, Ph.D.Assistant Professor
- DFP (Design For Power) VLSI chip design and automation for low power; and DFM (Design for Manufacturing) process variation and thermal effects analysis, and electrical verification for noise margin, IR drop, and signal EM (electro-migration).
- Ph.D. ECE, Georgia Institute of Technology, 2003
- Post Doctoral Research Associate, Sakurai Lab., University of Tokyo, 2005
Dr. Ken Choi joined the department of Electrical and Computer Engineering at IIT in the fall of 2007. He was a senior CAD engineer and a technical consultant for ultra-low-power SOC (system-on-chip) design in Samsung and Sequence Design prior to joining IIT. His research interests include DFP (Design For Power) VLSI chip design and automation for low power; and DFM (Design for Manufacturing) process variation and thermal effects analysis, and electrical verification for noise margin, IR drop, and signal EM (electro-migration).
Kyung Ki Kim, Haiqing Nan, and K-w Choi, "Ultra-Low Voltage Power Gating Structure Using Low Threshold Voltage", IEEE Tran. Circuits and Systems II, Vol. 56, Issue 12, Dec 2009
Kyung Ki Kim and K-w Choi, "On-chip Process Variation Monitoring Circuit based on Gate Leakage Sensing", IET Electronics Letters, Vol. 46, Issue 3, pp. 227-228, Feb. 2010
Feng Ge and Ken Choi “High Sensitivity UHF RFID Reader Baseband Design for EPC Class-1 Genration-2,” RFID Conference, April 14-16, 2010
Feng Ge and Ken Choi “Novel Design and Implementation for Highly Sensitive Baseband Protocol of Class-1 Generation-2 UHF RFID System,” IEEE EIT Conference, May 2010
Li Li and Ken Choi “SeSCG: Selective Sequential Clock Gating for Ultra-low-Power Multimedia Mobile Processor Design,” IEEE EIT Conference, May 2010
Wei Wang and Ken Choi “Novel Cruve Fitting Design Methodology to Optimize Carbon Nanotube SRAM Cell,” IEEE EIT Conference, May 2010
Haiqing Nan and Ken Choi “Novel CNFET SRAM Cell Design Operating in Sub-threshold Region Using Back-Gate Biasing,” IEEE EIT Conference, May 2010
Kyung Ki Kim, Haiqing Nan, Ken Choi, "Power Gating for Ultra-Low Voltage Nanometer ICs", IEEE ISCAS, May 30-June 2, 2010.
Kyung Ki Kim, Haiqing Nan, Ken Choi, "Adaptive HCI-aware Power Gating Structure", IEEE ISQED, March 22-24, 2010.
NamSung Kim and K-w Choi, and et. al., “Frequency and Yield Optimization using Power Gates in Power-Constrained Designs,” IEEE-ACM ISLPED (International Symposium on Low Power Electronics and Design 2009), San Francisco, CA, August 19-21, 2009
Li Li and K-w Choi, “Selective Power Gating using Wasting Toggle Rate for Ultra-Low Power Processor Design,” IEEE EIT, p64-69, Ontario, Canada, 2009
Feng Ge, Pranjal Jain and K-w Choi, “Ultra-Low Power and High Speed Design and Implementation of AES and SHA1 Hardware Cores in 65 Nanometer CMOS Technology,” IEEE EIT, p127-132, Ontario, Canada, 2009