Reconfigurable Computing Machines
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Course Objectives: 

This course deals with the implementation aspects of Computer Architecture. To cope 
with the complexity of a CPU, we introduce an industrial standard hardware 
description language- VHDL (IEEE-1076). This course begins with a summary of syntax 
of VHDL and hardware modelling techniques. The application of VHDL to top-down 
design methodology is presented. Students get familiar with a commercially available
VHDL tool through weekly hands-on laboratory assignments. The practical aspects of 
the implementation are introduced. The principles of design verification, test 
generation and Build-In-Self-Test (BIST) are presented. The course will be supported 
by the Altera-VHDL software and hardware. The laboratory portion of the course 
consists of eleven distinct projects designed, simulated, implemented and tested by
the student.

Prerequisites: 

       EE 218  Introduction to Logic Design
and    CS 350  Computer Organization
 

Text book: Computer Organization & Design, by D. Patterson & J. Hennessy, Morgan 
           Kaufmann

Reference books: A VHDL Primer, by Jayaram Bhasker. Prentice Hall, 1992
     VHDL Analysis and Modeling of Digital Systems, by Z. Navabi, McGraw-Hill, 1993
     VHDL Modeling for Digital Design Synthesis, by Yu-Chin Hsu, Kluwer, 1995
     Designer Guide VHDL Synthesis, by D. E. Ott, Kluwer, 1994

Projects:

There will be eleven project assignments throughout the course. The first eight
projects will be primarily to attune the students to the VHDL language. The next 
three projects (ALU, Barrel Shifter and Opcode decoder & sign extender) will be 
a real subsystem design. The final project will be a CPU design which will exploit 
the modular and hierarchical design approach in VHDL. The students are encouraged 
to combine the projects with those undertaken in other courses or work-related
projects. Projects will be implemented through the CPLD tools - Altera's MAXPLUS2.
A written presentation of the project results is required.

Grading:
       Projects and project reports:   50% 
       Exams:  50% 


Instructor:    Dr. Morris Chang
       Office: SB-228C (Main Campus)
       Tel: 312-567-5329
       email: chang@charlie.iit.edu    http://www.iit.edu/~chang
       Office Hours: Monday 1:00pm-3:00pm

       TA: Chia-Tien Dan Lo (lochiat@charlie.iit.edu) 
 office hours:  Wednesday 1:00-3:00 pm in 112I 

 








Syllabus:

Week             Material                Lab Assignment        

1                VHDL Dataflow          Binary Adder

2                VHDL Dataflow &         Logic Unit
        Multiplexing and Data Selection

3                VHDL Behavioral        Sequential System

4                VHDL Process &         Stepping Motor Controller
          Architecture of Altera CPLD

5                VHDL Process           Algorithmic State Machine (ASM)

6                VHDL Structural        Digital Comparator

7                VHDL Structural & Library      Multiplier

8                Midterm                Midterm project

9               Instruction Set & ALU   ALU for MIPS instructions

10               Shift Instructions     Barrel Shifter & Shifter

11              Datapath & Opcode       Opcode decoder & sign extender

12              High Performance CPU    Project

13              Hardware/software codesign      Project

14              Algorithm Mapping       Project

15              Cost Performance/Tesing Project Demonstration